Recently, since demands on a flash memory greatly increase in consumer electronics and mobile electric devices, a market of the flash memory is expected to exceed a market of an existing DRAM in 2007. Therefore, a memory device with a high integration degree and a short write/erase time has been required. The integration degree of a NAND flash memory has been required to increase, as IT techniques are developed. The integration degree of the NAND flash memory greatly depends on an integration degree of cell devices constituting the memory. Recently, a length of each cell device constituting the NAND flash memory decreases below 50 nm, and a total capacity of the memory reaches tens of gigabits. Accordingly, a short channel effect becomes a big problem in the NAND flash device having a planar channel structure including an existing conductive floating gate, and thus, there is a limitation to reduce the gate length. In addition, demands on a multi-level cell have been increased. Since the short channel effect due to device miniaturization increases dispersion of a threshold voltage in the multi-level cell, there is a limitation or impossibility to use the multi-level cell.
In order to improve the integration degree of the NAND flash memory, the gate length needs to be reduced. Therefore, in order to solve the problem, other alternative techniques have to be considered. As an alternative technique, in order to increase an integration degree of a device having an existing floating poly-electrode, an SONOS flash memory cell that uses an insulating storage electrode such as a nitride layer as a memory storage node is considered. In addition, a nano-floating gate memory (NFGM) that uses nano-sized dots (or nano-sized crystals) as a storage electrode is considered. In a case where a memory cell is embodied by forming a storage electrode such as nano-sized dots or a nitride layer on an existing planar channel structure, miniaturization characteristics can be improved in comparison with a case where an existing conductive poly-silicon floating gate is used. However, although the improved storage electrode is used, in a case where the gate length is equal to or less than 40 nm, it is difficult or impossible to miniaturize a memory cell due to a short channel effect.
In order to suppress the short channel effect caused in a case where a gate length of a cell device decreases below 40 nm and reduce a dispersion of a threshold voltage, an SONOS (or TANOS: TaN—AlO—SiN-Oxide-Si) cell device having an asymmetric source/drain structure on a planar channel device is proposed by Samsung Electronics Co., Ltd (K. T. Park et al, A 64-cell NAND flash memory with asymmetric S/D structure for sub-40 nm technology and beyond, in Technical Digest of Symposium on VLSI Technology, p. 24, 2006).
In the aforementioned structure, with respect to a gate of a cell device, there is a region corresponding to a source or drain in the one side of the cell device, and there is no source or drain in the other side thereof. In the structure, the short channel effect is suppressed by forming an inversion layer using a fringing field from a control electrode in a region where there is no source or drain. Although in the aforementioned structure, a miniaturization characteristic is improved in comparison with an SONOS cell device having a planar channel and an existing source/drain region, the short channel effect occurs in a channel length equal to or less than 40 nm. As a result, there is a limitation to miniaturize a cell device having a planar channel structure.
In addition, a flash device structure in which a channel is recessed and a conductive floating gate is used as a storage electrode so as to reduce the short channel effect occurring in the existing planar channel structure is proposed by Samsung Electronics Co., Ltd. (S.-P. Sim et al, Full 3-dimensional NOR flash cell with recessed channel and cylindrical floating gate—A scaling direction for 65 nm and beyond, in Technical Digest of Symposium on VLSI Technology, p. 22, 2006). However, as the device is miniaturized, the width of a recessed region needs to be reduced. Accordingly, there is a problem in that characteristics of the device deteriorate, and non-uniformity of the device increase.
The inventor of the present invention firstly proposed a double/triple-gate flash memory cell structure formed on an SOI substrate (see Korean Patent No. 10-431-489 and U.S. Pat. No. 6,768,158 B2) a body-tied double/triple-gate flash memory cell structure formed on a bulk substrate (see Korean Patent No. 10-420070 and U.S. patent application Ser. No. 10/751,860). In the double/triple-gate structure proposed by the inventor, a gate electrode surrounds a gate structure region so as to improve a controllability of the gate electrode to the channel. The structure is referred to a bulk fin field effect transistor (bulk FinFET) by the inventor. In the structure, the channel is formed in an upper surface and both side surfaces of a wall-shaped body having a shape protruding from a substrate, or the channel is formed at both sides of the wall-shaped body, so that the controllability of the gate electrode to the channel can be improved in comparison with an existing planar channel device.
Hereinafter, a structure and operations of the aforementioned double/triple-gate device proposed by the inventor will be described with reference to FIG. 1. In FIG. 1, (a) is a three-dimensional perspective view illustrating a double/triple metal oxide semiconductor (MOS) device formed on a bulk substrate, (b) is a cross-sectional view taken along line B-B′, and (c) is a cross-sectional view taken along line A-A′. As shown in FIG. 1, the double/triple-gate device 10 include a bulk silicon substrate 100, a wall-shaped body 110, an isolation insulating layer 120, a tunneling insulating layer 130, a gate electrode 140, and source/drain regions 150.
The wall-shaped body 110 is formed by patterning the bulk silicon substrate 100 in a wall shape having predetermined height, width, and length. The isolation insulating layer 120 is made of an electrically insulating material and formed up to a surface of the substrate and a predetermined height of the wall-shaped body, so as to electrically isolate devices to be formed on the substrate 100. The tunneling insulating layer 130 formed on side walls and the upper surface of the wall-shaped body that protrude over the isolation insulating layer. The gate electrode 140 is formed on the gate insulating layer and the insulating layer in a direction perpendicular to a longitudinal direction of the wall-shaped body. The source/drain regions 150 are formed in regions of the wall-shaped body where the gate electrode is not formed.
In the double/triple-gate device having the aforementioned construction, the channel of the device is formed on the surface and side surfaces of the wall-shaped body 110 protruding over the isolation insulating layer 120, and the gate electrode 140 is formed on the surface and side surfaces of the protruding wall-shaped body, so that the controllability to the channel can be greatly improved. As a result, the miniaturization characteristics of the device can be improved, and the write/erase characteristics can be also improved. However, as the gate length of the cell device gradually decreases below 40 nm, the short channel effect is still remained although it is smaller than the short channel effect of the planar channel structure. Therefore, there is a need for solving the problem of the short channel effect.
Accordingly, in order to solve the problems of the aforementioned existing devices, a flash memory device having a high degree of integration and high performance with a new structure capable of suppressing the short channel effect and deterioration in performance needs to be developed.